High-Speed Low-Power Approach for Implementation of 8B/10B Encoder for High-Speed Communications
AbstractIn this paper, the design methodology for a high-speed 8B/10B encoding architecture has been discussed. By means of the new truth table and with the help of Pass-Transistor Logic (PTL), a new structure has been designed in CMOS technology, which shows a superior speed performance. Also, power consumption is optimized because of careful design considerations. These features, along with the simplicity of the employed circuitry are the quality of this work to be repeatedly used in high-speed communication systems. The design process has been explained in detail so that the idea can completely be understood. Moreover, the proposed structure has been demonstrated in the circuit level for better clarification. Post-layout simulation results for TSMC 0.18µm standard CMOS technology depict the correct behavior of the proposed architecture whilst the power consumption is 1.64mW from 1.8v power supply.
 J. Kathuria, M. Ayoubkhan, and A. Noor, “A Review of Clock Gating Techniques,” MIT International Journal of Electronics and Communication Engineering, Vol. 1, No. 2, pp. 106-114, 2011.
 K. Sahni, K. Rawat, and S. Pandey, “Power optimization of 8b/10b encoder decoder used for high speed communication,” 9th International Conference on Industrial and Information Systems (ICIIS), Gwalior, India, 2014.
 A.X. Widmer, and P.A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code,” IBM Journal of Research and Development, Vol. 27, No. 5, pp. 440-451, 1983.
 Y. Takasaki, M. Tanaka, N. Maeda, K. Yamashita, and K. Nagano, “Optical Pulse Formats for Fiber Optic Digital Communications,” IEEE Transactions on Communications, Vol. 24, No. 4, pp. 404-43, 1976.
 X. Qiaoyu, and L. Huijie, “8b/10b Encoder Design,” The 2nd International Conference on Computer Application and System Modeling, Paris, France, 2012.
 Z. Cai, J. Hao, P.H. Tan, S. Sun, and P.S. Chin, “Efficient encoding of IEEE 802.11n LDPC codes,” Electronics Letters, Vol. 42, No. 25, pp. 1471-1472, 2006.
 M. Maadi, “An 8b/10b Encoding Serializer/Deserializer (SerDes) Circuit for High Speed Communication Applications Using a DC Balanced, Partitioned-Block, 8b/10b Transmission Code,” International Journal of Electronics and Electrical Engineering, Vol. 3, No. 2, pp. 144-148, 2015.
 “8b/10b Encoder/Decoder,” Lattice Semiconductor Reference Design RD1012, 2015.
 G.S. Solanki, R. Agarwal, and S. Sharma, “Power Optimization of High Speed Pipelined 8B/10B Encoder,” International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 3, No. 7, pp. 14-16, 2013.
 K. Odaka, “Method and apparatus for encoding binary data,” U.S. Patent 4456905, 1984.
 P.A. Franaszek, and A.X. Widmer, “Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code,” U.S. Patent 4486739, 1984.
 K.A.S. Immink, “Method of transmitting information, encoding device for use in the method, and decoding device for use in the method,” U.S. Patent 4620311, 1986.
 “8B/10B Encoder v5.0”, Xilinx, Logicore, 2004.
 Y. Kim, and J. Kang, “An 8B/10B encoder with a modified coding table,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2008.
 Q. Wang, S. Hua, and D. Wang, “A 1.1 GHz 8B/10B encoder and decoder design,” Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010.
 J. Thatcher, “Thoughts on Gigabit Ethernet Physical,” IBM, Retrieved 2008-08-17, 1996.
 A. Fathi, S. Azizian, K. Hadidi, and A., Khoei, “A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations,” IEICE Transactions on Electronics, Vol. 95, No. 4, pp. 710–712, 2012.
 A. Fathi, S. Azizian, K. Hadidi, A. Khoei, and A. Chegeni, “CMOS Implementation of a Fast 4-2 Compressor for Parallel Accumulations,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1476–1479, 2012.