Variable Latency Speculative Multiply-Accumulator Architectures

  • Hoda Ghabeli Kerman Branch, Islamic Azad University
  • Amir Sabbagh Molahosseini Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Kerman, Iran
  • Azadeh Alsadat Emrani Zarandi Shahid Bahonar University of Kerman
Keywords: Integration Technique, Multiply-Accumulator, Partial-Product, Variable Latency Speculative Circuits


In this paper, variable latency speculative Multiply-Accumulator (MAC) architectures are introduced. The proposed architectures use the idea of integrating the results vectors of multiplier in parallel with the accumulator to create asynchronous data paths design. The proposed variable latency speculative MACs consist of two short and long data paths and a circuit is used to select a suitable path with minimum overhead. In order to investigate variable latency speculative MACs performances, proposed architectures have been synthesized using the Faraday’s 90 nm technology library, for operand lengths 8, 16 and 32 bits. Obtained results show that the proposed MAC architectures provide a variety of trade-offs in the power-delay-area space that outperform the existing designs that use only the integration technique.

Author Biography

Amir Sabbagh Molahosseini, Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Kerman, Iran
Amir Sabbagh Molahosseini was born in Kerman, Iran, in 1983. He received the B.Sc. degree in computer engineering from Shahid Bahonar University of Kerman, Iran in 2005. He also received his M.Sc. and Ph.D. degrees in computer engineering from Islamic Azad University, Science and Research Branch, Tehran, Iran in 2007 and 2010, respectively. He is currently an Assistant Professor in the Department of Computer Engineering, Islamic Azad University, Kerman Branch, Kerman, Iran. His research interests include VLSI design and computer arithmetic.


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How to Cite
Ghabeli, H., Sabbagh Molahosseini, A., & Emrani Zarandi, A. A. (2022). Variable Latency Speculative Multiply-Accumulator Architectures. Majlesi Journal of Electrical Engineering, 16(2). Retrieved from