Crosstalk Enhancement in 32 nm FD SOI MOSFET using HR Substrate and Multilayer BOX

  • Parisa Tavanazadeh
  • Arash Daghighi
  • Homayoun Mahdavi-Nasab
Keywords: ultra thin body silicon-on-insulator MOSFET, parasitic capacitance, high resistivity substrate, crosstalk, diamond


In this paper, the crosstalk in 32 nm UTB SOI MOSFET is examined by using a new structure, a high resistivity substrate, and a multilayer BOX (SiO2-Diamond). The electrical and thermal characteristics of the conventional SOI and a multilayer BOX SOI are compared, and it is concluded that parasitic capacitances and crosstalk are improved by incorporating multilayer BOX to a HR Substrate. In a conventional HR FD SOI, crosstalk is approximately -121dB, while by incorporating multilayer BOX substrate and increasing the thickness of the Diamond to 100nm, crosstalk can be reduced by 20%.

Author Biographies

Parisa Tavanazadeh
M.Sc student, Islamic azad university,najaf abad baranch
Arash Daghighi
Assistant professor, faculty of Engineering, shahrekord University
Homayoun Mahdavi-Nasab
Assistant professor, faculty of Engineering, Islamic azad university,najaf abad baranch


[1] T. Sakuria, A. Matsuzawa and T. Douseki, “Fully-Depleted SOI CMOS Circuit and technology for ultra low power application”, springer, 2006.

[2] H. Ghanatian, M. Fathipour and H. Talebi, “Nanoscale Ultra Thin Body-Silicon-On-Insulator Field Effect Transistor with Step BOX: Self-heating and Short Channel Effects”, IEEE/ULIS, pp.325-328, Aachen, 2009.

[3] Y.-T. Hou, M.-F. Li, T. Low, D.-L. Kwong, “Metal Gate Work Function Engineering on Gate Leakage of MOSFETs”, IEEE Transaction on electron devices, vol.51, No.11, pp. 1783-1789, November 2004.

[4] J. Ankarcrona , L. Vestling, K.-H Eklund and J. Olsson, “Efficient Crosstalk Reduction Using Very Low Resistivity SOI Substrate”, IEEE/ESSDERC, pp.233-236, France, 2005.

[5] B.A. Khaled, C.R. Neve, A. Gharsallah and J.-P. Rskin, “Efficient Polysilicon Passivation Layer for Crosstalk Reduction in High-Resistivity SOI Substrate”, IEEE/SiRF, pp.212-215, New Orleans, Jan 2010.

[6] JP. Coling, “Silicon-On-Insulator Technology Material to VLSI”, Kluwer Academic Publishers, 2004.

[7] User manual for ISE TCAD.

[8] J.A Luna-Lopez, M. Aceves-Mijares, O. Malik and R. Glaenzer, “Modelling the C-V characteristics of MOS capacitor on high resistivity silicon substrate for PIN photo detector applications”, Rev.Mex.Fis.S52, pp.45-47, Febrero 2006.

[9] K. Raleva, D. Vasileska and S. Goodnick, “Is SOD Technology the Solution to Heating problems in SOI Devices?”,IEEE ELECTRON DEVICE LETTERS,vol.29,No.6,JUNE 2008.
How to Cite
Tavanazadeh, P., Daghighi, A., & Mahdavi-Nasab, H. (2011). Crosstalk Enhancement in 32 nm FD SOI MOSFET using HR Substrate and Multilayer BOX. Majlesi Journal of Electrical Engineering, 5(2). Retrieved from