Non-Blocking and Multi Wavelength Optical Router Design based on Mach-zehnder Interferometer in 3-D Optical Network on Chip

  • Sanaz Asadinia Department of Computer Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran.
  • Mahdi Mehrabi Department of Computer Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran.
  • Elham Yaghoubi Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran.
Keywords: Insertion Loss, Non-blocking, Mach-Zehnder Interferometer (MZI), Optical Router, 3D Optical Network on Chip (3D-ONoC), Power Consumption, Wavelength Division Multiplexing (WDM)


Due to the increasing number of cores in a chip, electronic networks on chip cannot be an effective solution for using multi-core processors. The use of optical connection technology for networks on 3D chip is an ideal choice recommended in response to delay and reliability. In optical network architecture on 3D chip, 7-port routers are used to data transfer. The structure of the optical routers in the network on the 3D optical chip affects the Performance transmission of the entire network so that the provision of optical router with minimal loss and power consumption is considered by researchers in this domain. In this study, a seven-port Non-blocking optical router based on the Mach Zehnder interferometer optical switch in the network on a 3-D optical chip is presented. This router consists of 18 Mach Zehnder interferometer optical switches that can transfer multiple wavelengths concurrently. To evaluate the proposed 7-port router in the network on the 3D optical chip, the parameters of insertion loss, bandwidth density and power consumption are considered and the simulation results represent that this router decreases the loss as much as possible and improves the use of the wavelength channel comparing to available router and has the ability to transfer 4 wavelengths simultaneously with a wavelength range of 1525-1565 nm and a data transfer rate of 20Gbps for all 42 optical links. So it is useable for optical connection on the chip.


1. W. Wolf, A. A. Jerraya, G. Martin, "Multiprocessor system-on-chip (MPSoC) technology", IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol. 27, no. 10, pp. 1701-1713, Oct. 2008.
2. Kulkarni et al., "An energy-efficient programmable manycore accelerator for personalized biomedical applications", IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 26, no. 1, pp. 96-109, Jan.2017.
3. K. Bergman, L. P. Carloni, A. Biberman, J. Chan, and G. Hendry, Photonic network-on-chip design: Springer, 2014.
4. Liu, et al., “Wavelength-Reused Hierarchical Optical Network on Chip Architecture for Many core Processors”, IEEE Transactions on Sustainable Computing, vol. 4, no. 2, pp. 231-244. 2019.
5. Y. Ye et al., “3-D mesh-based optical network-on-chip for multiprocessor system-on-chip,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 32, no. 4, pp. 584–596, Apr. 2013.
6. K. Zhu, H. Gu, Y. Yang, W. Tan, and B. Zhang, “A 3D multilayer optical network on chip based on mesh topology,”Photon. Netw. Commun. vol. 2016, no. 3, pp. 293–299, 2016.
7. H. Gu and J. Xu, “Design of 3D Optical Network on Chip,” in Proc. IEEE Symp. Photon. Optoelectronics, 2009, pp. 1–4.
8. J. H. Lau, Through-Silicon Vias for 3D Integration. New York, NY, USA: McGraw-Hill, 2012, ISBN-13 978-0071785143.
9. M. Segev and A. Szameit," Introduction to Photonic Topological Insulators", AMOLF Nanophotonics Summer School, June 2019
10. Guo P, Hou W, Guo L, Yang Q, Ge Y, Liang H (2018) Low Insertion Loss and Non-Blocking Microring-Based Optical Router for 3D Optical Network-on-Chip. IEEE Photonics Journal. DOI:10.1109/JPHOT.2018.2796094
11. G. Dimitrakopoulos, A. Psarras, I. Seitanidis, “Microarchitecture of network-on-chip routers, a designer's perspective”, Springer Press, New York,NY, USA, 2015.
12. L. Lu, L. Zhou, Z. Li, X. Li, J. Chen, "Broadband 4× 4 non-blocking silicon electro optic switches based on Mach–Zehnder interferometers", IEEE Photon.J., vol. 7, no. 1, Feb. 2015.
13. M. Bahadori, S. Rumley, R. Polster, and K. Bergman, “Loss and crosstalk of scalable MZI-based switch topologies in silicon photonic platform,” in 2016 IEEE Photonics Conference (IPC), 2016, pp.615-616.
14. N. Dupuis et al., "Design and fabrication of low insertion-loss and low-crosstalk broadband 2 × 2 Mach–Zehnder silicon photonic switches", J.Lightw. Technol., vol. 33, no. 17, pp. 3597-3606, Sep. 2015.
15. E. Fusella and A. Cilardo, “H2ONoC: A hybrid optical–electronic NoC based on hybrid topology”,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 330-343, 2017.
16. R. Cao, Y. Yang, H. Gu, and L. Huang, “A thermal-aware power allocation method for optical network-on-chip,” IEEE Access, vol. 6, pp. 61176–61183, 2018.
17. T. Zhou, H. Jia, J. Dai, S. Yang, L. Zhang, X. Fu,L. Yang, "Rearrangeable-nonblocking five-port silicon optical switch for 2-D-mesh network on chip", IEEE Photon. J., vol. 10, no. 3, Jun. 2018.
18. J. H. Lee, et al., “Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based Optical Network-on-Chip”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37. No. 3, pp. 559-572. Mar. 2018.
19. M. Rehan Yahya, et al., “HoneyComb ROS: A 6 ×6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs”, Elcteronics., July.2019.
20. T. Alexoudi, et al., “Optics in computing: From photonic network-on-chip to chip-to-chip interconnects and disintegrated architectures,” Journal of Lightwave Technology, vol. 37, no. 2, pp. 363-379,Jan 2019.
21. T. Zhou and H. Jia, “Method to optimize optical switch topology for photonic network-on-chip, "Opt. Commun., vol. 413, pp. 230_235, Apr. 2018.
22. Y. Wu, C. Lu, AND Y. Chen, “A Survey of routing algorithm for mesh network-on-chip,” Frontiers of computer science, vol. 10, pp. 591-601, 2016.
23. J. Chan, A. Biberman, B. G. Lee, and K. Bergman, “Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications,”Proc. 21st Ann. Meeting of the IEEE Lasers and Electro-Optics Society(LEOS), pp. 300-301,2008.
24. Geng, M.; Tang, Z.; Chang, K.; Huang, X.; Zheng,J. “N-port strictly non-blocking optical router based on Mach-Zehnder optical switch for photonic networks-on-chip”. Opt. Commun. 2017, 383, 472–477.
25. Zhao, Shuoyi, Liangjun Lu, Linjie Zhou, Dong Li,Zhanzhi Guo, and Jianping Chen. "16×16 silicon Mach–Zehnder interferometer switch actuated with waveguide microheaters." Photonics Research 4, no. 5 (2016): 202-207.
26. Elham Yaghoubi and M. Reshadi, "Five-Port Optical Router Design Based on Mach–Zehnder Switches for Photonic Networks-on-Chip," Journal of Advances in Computer Research, vol. 7, pp. 47-53, 08/01 2016.
27. Yaghoubi, E.; Reshadi, M.; Hosseinzadeh, M."Mach–Zehnder-based optical router design for photonic networks on chip". Opt. Eng. 2015, 54,035102.
28. Yunchou Zhao, Hao Jia, Jianfeng Ding, Lei Zhang, Xin Fu, and L. Yang, "Five-port silicon optical router based on Mach—Zehnder optical switches for photonic networks-on-chip," Journal of Semiconductors, vol. 37, p. 114008, 2017.
29. R. A. Spanke and V. E. Benes, "N-stage planar optical permutation network," Applied Optics, vol. 26, pp. 1226-1229, 1987/04/01 1987.
30. T. Zhou, H. Jia, J. Dai, S. Yang, L. Zhang, X. Fu, et al., "Rearrangeable-Nonblocking Five-Port Silicon Optical Switch for 2-D-Mesh Network on Chip," IEEE Photonics Journal, vol. 10, pp. 1-8, 2018.
31. Hao J, Ting Zh, Yunchou Zh, Yuhao X, Jincheng D, Lei Zh, Jianfeng D, Xin F and Lin Y, "Six-port optical switch for cluster-mesh photonic network-on-chip", Nanophotonics; 7(5): 827–835,2018
32. Yang, Min, William MJ Green, Solomon Assefa,Joris Van Campenhout, Benjamin G. Lee, Christopher V. Jahnes, Fuad E. Doany, Clint L. Schow, Jeffrey A. Kash, and Yurii A. Vlasov. "Non- blocking 4x4 electro-optic silicon switch for on-chip photonic networks." Optics express 19, no.1 (2011): 47-54.
33. Geng, M., Tang, Z., Chang, K., Huang, X., Zheng, J. "N-port strictly non-blocking optical router based on Mach-Zehnder optical switch for photonic networks-on-chip," Optics Communications, Vol. 383, No. pp. 472-477, 2017.
34. Freude, W., Schmogrow, R., Nebendahl, B., Winter, M., Josten, A., Hillerkuss, D., Koenig, S., Meyer, J., Dreschmann, M., Huebner, M., Koos, C., Becker, J., Leuthold, J. "Quality metrics for optical signals: Eye diagram, Q-factor, OSNR, EVM and BER," 2012 14th International Conference on Transparent Optical Networks (ICTON), pp. 1-4, 2-5 July 2012.
35. Breed and Gray, "Analyzing signals using the eye diagram," High Frequency Electronics, vol. 4, pp. 50--53, 2005.
36. F. Xia, L. Sekaric, & Y. Vlasov. (2006). Ultracompact optical buffers on a silicon chip, Nature Photonics, 1, 65–71.
How to Cite
Asadinia, S., Mehrabi, M., & Yaghoubi, E. (2021). Non-Blocking and Multi Wavelength Optical Router Design based on Mach-zehnder Interferometer in 3-D Optical Network on Chip. Majlesi Journal of Electrical Engineering, 15(2), 73-81.