Design of a 16-by-16-bit Unsigned Serial-parallel Multiplier using Retime Technique
AbstractIn this paper, the structure of a 16-by-16 unsigned hybrid (serial-parallel) multiplier has been proposed. Parallel multipliers, in comparison with serial multipliers, have higher speed and higher power consumption. In hybrid structures, to reduce power and increase speed, both serial and parallel techniques are used. The proposed structure improves propagation delay and reduces power consumption using pipeline and retime techniques. Simulation results show that it has 5.7 ns propagation delay and 2.65 mW power consumption. The figure of merit for energy consumption is 15.2 PJ. The proposed multiplier has been designed using 0.18 μm TSMC process at 1.8 V supply and simulated using Cadence tools. The layout of the multiplier occupies 52414 μm2.
 C. Chinmay, B. Gupta, and S. K. Ghosh, “A Review on Telemedicine-Based WBAN Framework for Patient Monitoring,” Telemedicine and e-Health, vol. 19, no. 8, pp. 619–626, Aug, 2013.
 S. Minhyeok, and H. Lee, “A high-speed four-parallel radix-2 4 FFT/IFFT processor for UWB applications,” Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on. IEEE, 2008.
 L. Jeesung, and H. Lee, “A high-speed two-parallel radix-2 4 FFT/IFFT processor for MB-OFDM UWB systems.” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 91, no. 4, pp. 1206-1211, 2008.
 T. Cho, and H. Lee, “A High-Speed Low-Complexity Modified Radix-25 FFT Processor for High Rate WPAN Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(1), pp.187-191, 2013.
 A. Pishvaie, G. Jaberipur, and A. Jahanian, “Improved CMOS (4; 2) compressor designs for parallel multipliers,” Comput. Elect. Eng., vol. 38, no. 6, pp. 17031716, Nov. 2012.
 D. Baran, M. Aktan, and V. G. Oklobdzija, “Energy efficient implement- tion of parallel CMOS multipliers with improved compressors,” in Proc. ACM/IEEE Int. Symp. Low-Power Electron. Design (ISLPED), pp. 147152, 2010.
 A. R. Cooper, “Parallel architecture modified Booth multiplier,” In IEE Proceedings G (Electronic Circuits and Systems) (Vol. 135, No. 3, pp. 125-128). IET Digital Library
 Y. Wen-Chang, and C. W. Jen. “High-speed Booth encoded parallel multiplier design,” IEEE transactions on computers, vol. 49, no. 7, pp. 692-701, 2000.
 T. Jin-Hao, and L. D. Van, “Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers,” IEEE transactions on computers, vol. 58, no. 10, pp. 1346-1355, 2009.
 W. Chua-Chin, and G. N. Sung, “Low-power multiplier design using a bypassing technique,” Journal of Signal Processing Systems vol. 57, no. 3, pp.331-338, 2009.
 B. Hung Tien, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. vol. 49, no. 1, pp.25-30, 2002.
 M. M. Ranjan, C. C. Jong, and C. Chang, “A high bit rate serial-serial multiplier with on-the-fly accumulation by asynchronous counters,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol.19, no.10: pp.1733-1745, 2011.
 G. Maged, et al. “Serial-link bus: A low-power on-chip bus architecture,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 9, pp. 2020-2032, 2009.
 R.R. Dobkin, A. Morgenshtein, A. Kolodny, and R. Ginosar, “Parallel vs. serial on-chip communication,” In Proceedings of the 2008 international workshop on System level interconnect prediction (pp. 43-50). ACM.
 C. Brian S., and E. G. Friedman. “A hybrid radix-4/madix-8 low power signed multiplier architecture,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 8, pp. 656-659, 1997.
 T. Somsubhra, H. Rahaman, and J. Mathew, “Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF” IEEE transactions on very large scale integration (VLSI) systems, vol. 18, no. 5, pp. 847-852, 2010.
 X. Jiafeng, P. K. Meher, and J. He. “Low-latency area-delay-efficient systolic multiplier over GF (2 m) for a wider class of trinomials using parallel register sharing,” Circuits and Systems (ISCAS), 2012 IEEE International Symposium on. IEEE, 2012.
 S. Choi, et al. “Hybrid radix-4/-8 truncated multiplier for mobile GPU applications,” Electronics Letters, vol.50, no. 23, pp. 1680-1682, 2014.
 M. P. Kumar, et al. “Low-Cost Design of Serial-Parallel Multipliers Over GF (2m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic,” Electronic System Design (ISED), 2010 International Symposium on. IEEE, 2010.
 N. Jagadeeshkumar, and D. Meganathan, “A novel design of low power and high speed hybrid multiplier,” Signal Processing, Communication and Networking (ICSCN), 2017 Fourth International Conference on. IEEE, 2017.
 B. Hung Tien, Y. Wang, and Y. Jiang. “Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. vol. 49, no. 1, pp. 25-30, 2002.
 Y. Sung-Hyun, Y. You, and K. R. Cho, “A new dynamic D-flip-flop aiming at glitch and charge sharing free,” IEICE transactions on electronics, vol. 86, no. 3, pp. 496-505, 2003.
 B. R. Zeydel, D. Baran, and V. G. Oklobdzija, “Energy-efficient design methodologies: High-performance VLSI adders,” IEEE Journal of solid-state circuits, 45(6), pp.1220-1233.
 K. Dey, and S. Chattopadhyay, “Design of high performance 8 bit binary multiplier using vedic multiplication algorithm with 16 nm technology,” In Electronics, Materials Engineering and Nano-Technology (IEMENTech), 2017 1st International Conference on (pp. 1-5). IEEE.
 G. Kim, S. Lee, J. Park, and H. J. Yoo, “A low-energy hybrid radix-4/-8 multiplier for portable multimedia applications,” In Circuits and Systems,” (ISCAS), 2011 IEEE International Symposium on (pp. 1171-1174). IEEE.