Power Reduction of the Low Offset Dynamic Comparator with Novel Techniques

  • Mousa Yousefi Azarbijan Shahid Madani University
  • Khalil Monfaredi
Keywords: Efficiency, Low-power, Comparator, Low-offset, Dynamic

Abstract

In this paper, dynamic comparators structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparators have low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparators consume 14.3 and 24 μW at 100 MHz which is equal to 3.7 and 11.8 fJ. The comparators have been designed and simulated in 180 nm CMOS. Layouts occupy 210 and 240 μm2, respectively.

References

[1] Y. L. Wong, M. H. Cohen, & P. A. Abshire, A 1.2-GHz comparator with adaptable offset in 0.35-m CMOS. Circuits and Systems I: Regular Papers, IEEE Transactions on, no. 55, vol. 9, pp. 2584-2594, 2008.
[2] K. Uyttenhove, & M. S. Steyaert, Speed-power-accuracy tradeoff in high-speed CMOS ADCs. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 49, no.4 , pp. 280-287, 2002.
[3] B. Razavi, & B. A. Wooley, Design techniques for high-speed, high-resolution comparators. Solid-State Circuits, IEEE Journal of, vol. 27, pp. 1916-1926, 1992.
[4] H. Gao, P. Baltus, & Q. Meng, Low voltage comparator for high speed ADC, In Signals Systems and Electronics (ISSSE), 2010 International Symposium on vol. 1, pp. 1-4, 2010.
[5] J. He, S. Zhan, D. Chen, & R. L. Geiger, Analyses of static and dynamic random offset voltages in dynamic comparators. Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 56, pp.911-919, 2009.
[6] M. Kandala, & H. Wang, H. A 0.5 V high-speed comparator with rail-to-rail input range. Analog Integrated Circuits and Signal Processing, vol. 73, pp. 415-421. 2012.
[7] Z. Zhu, G. Yu, H. Wu, Y. Zhang, & Y. Yang, A high-speed latched comparator with low offset voltage and low dissipation, Analog Integrated Circuits and Signal Processing, vol. 74, pp. 467-471. 2013.
[8] T. B. Cho, & P. R. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter, Solid-State Circuits, IEEE Journal of, vol. 30, pp.166-172.1992.
[9] V. Katyal, R. L. Geiger, & D. J. Chen, A new high precision low offset dynamic comparator for high resolution high speed ADCs, In Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on pp. 5-8. 2006.
[10] M. Hassanpourghadi, M. Zamani, & M. Sharifkhani, A low-power low-offset dynamic comparator for analog to digital converters. Microelectronics Journal, vol. 45, pp. 256-262. 2014:
[11] M. J. Pelgrom, A. C. Duinmaijer, & A. P. Welbers, Matching properties of MOS transistors, IEEE Journal of solid-state circuits, vol. 24, pp.1433-1439. 1989.
[12] K. Uyttenhove, & M. S. Steyaert, Speed-power-accuracy tradeoff in high-speed CMOS ADCs, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol.49, pp.280-287, 2002.
[13] S. Babayan-Mashhadi, & R. Lotfi, Analysis and design of a low-voltage low-power double-tail comparator, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, pp. 343-352, 2014.
Published
2018-07-09
How to Cite
Yousefi, M., & Monfaredi, K. (2018). Power Reduction of the Low Offset Dynamic Comparator with Novel Techniques. Majlesi Journal of Electrical Engineering, 13(2). Retrieved from http://mjee.iaumajlesi.ac.ir/index/index.php/ee/article/view/2801
Section
Articles