Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector

  • Nagarjuna Telagam Institute of Aeronautical Engineering, Electronics and communication Engineering, Hyderabad, India http://orcid.org/0000-0002-6184-6283
  • Nehru Kandasamy Professor, Institute of Aeronautical Engineering, Electronics and communication Engineering, Hyderabad, India http://orcid.org/0000-0002-5673-0593
Keywords: HDL, FPGA, ALU, DECODER, DATA SELECTOR, CMOS, FINFET, POWER, AREA, SPEED.

Abstract

The semiconductor circuits dissipate energy in the form of binary digits. This dissipation of energy is in the form of power consumption. ALU is complex circuit and is one of many components within CPU. It performs mathematical and bitwise operations. This paper proposes a new low power 8 bit ALU digital circuit for nano scale regions. The proposed ALU has two 4x1 data selectors, 2x4 decoder and an adder circuit as sub modules. The output of 2x4 decoder is connected to 3 input NAND, AND, OR, XOR gates.  With the help of selection lines of multiplexer the conventional operations of ALU such as logical operations are performed. This proposed ALU caters the need of digital signal processing tools. Present ALU structure is simulated in Linux Computer using Cadence Virtuoso software and implemented in 180mm technology. The proposed ALU has delay of 386.0ps and average power of 677.2uW. The power delay product shows 65.58 % improvement when compared to the conventional 8-bit ALU design

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Published
2018-01-01
How to Cite
Telagam, N., & Kandasamy, N. (2018). Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector. Majlesi Journal of Electrical Engineering, 12(1), 103-108. Retrieved from http://mjee.iaumajlesi.ac.ir/index/index.php/ee/article/view/2346
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Articles