Performance Analysis of High Speed Radix-4 Booth Encoders in CMOS Technology

  • Nader Sharifi Gharabaghlo Urumi Graduate Institute
  • Tohid Moradi Khaneshan Urumi Graduate Institute
Keywords: Parallel Multiplier, Booth Encoder, Radix-4, High Speed


This review paper deals with performance analysis of the published works for circuit level realization of radix-4 Booth encoder/decoders. Starting from general concept of Booth algorithm in brief form, the conventional truth table is discussed. Subsequently, the modifications which led to the circuit level implementations along with the complete and comparative analysis for the selected works, is provided. Simulations using HSPICE for TSMC 0.18µm CMOS technology and 1.8V power supply have been performed for comparing these works. Considering the required optimizations applied to the mentioned works, it can be deduced that 1.5 XOR gate level delay is reachable for radix-4 Booth encoding scheme while the output waveforms are free of any glitches. The optimized version of Booth encoder has been embedded in a 16x16 bit parallel multiplier in which, the measured latency after post layout simulations is 1992ps; which demonstrates the high potential of chosen radix-4 Booth encoding scheme for utilization in high speed parallel multipliers.


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How to Cite
Sharifi Gharabaghlo, N., & Moradi Khaneshan, T. (2019). Performance Analysis of High Speed Radix-4 Booth Encoders in CMOS Technology. Majlesi Journal of Electrical Engineering, 13(3), 49-57. Retrieved from